? 2001 fairchild semiconductor corporation ds011347 www.fairchildsemi.com february 1992 revised june 2001 74lvq74 low voltage dual d-type positive edge-triggered flip-flop 74lvq74 low voltage dual d-type positive edge-triggered flip-flop general description the lvq74 is a dual d-type flip-flop with asynchronous clear and set inputs and complementary (q, q ) outputs. information at the input is transferred to the outputs on the positive edge of the clock pulse. clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. after the clock pulse input threshold voltage has been passed, the data input is locked out and information present will not be transferred to the outputs until the next rising edge of the clock pulse input. asynchronous inputs: low input to s d (set) sets q to high level low input to c d (clear) sets q to low level clear and set are independent of clock simultaneous low on c d and s d makes both q and q high features ideal for low power/low noise 3.3v applications guaranteed simultaneous switching noise level and dynamic threshold performance guaranteed pin-to-pin skew ac performance guaranteed incident wave switching into 75 ? ordering code: devices also available in tape and reel. specify by appending the suffix letter ?x? to the ordering code. logic symbols ieee/iec connection diagram pin descriptions order number package number package description 74lvq74sc m14a 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74lvq74sj m14d 14-lead small outline package (sop), eiaj type ii, 5.3mm wide pin names description d 1 , d 2 data inputs cp 1 , cp 2 clock pulse inputs c d1 , c d2 direct clear inputs s d1 , s d2 direct set inputs q 1 , q 1 , q 2 , q 2 outputs
www.fairchildsemi.com 2 74lvq74 truth table h = high voltage level l = low voltage level x = immaterial = low-to-high clock transition q 0 (q 0 ) = previous q(q ) before low-to-high transition of clock logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays. inputs outputs s d c d cp d q q lhxxhl hlxxlh llxxhh hh hhl hh llh hhl xq 0 q 0
3 www.fairchildsemi.com 74lvq74 absolute maximum ratings (note 1) recommended operating conditions (note 2) note 1: the ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the ? recommended operating conditions ? table will define the conditions for actual device operation. note 2: unused inputs must be held high or low. they may not float. dc electrical characteristics note 3: all outputs loaded; thresholds on input associated with output under test. note 4: maximum test duration 2.0 ms, one output loaded at a time. note 5: incident wave switching on transmission lines with impedances as low as 75 ? for commercial temperature range is guaranteed for 74lvq. note 6: worst case package. note 7: max number of outputs defined as (n). data inputs are driven 0v to 3.3v; one output at gnd. note 8: max number of data inputs (n) switching. (n ? 1) inputs switching 0v to 3.3v. input-under-test switching: 3.3v to threshold (v ild ), 0v to threshold (v ihd ), f = 1 mhz. supply voltage (v cc ) ? 0.5v to + 7.0v dc input diode current (i ik ) v i = ? 0.5v ? 20 ma v i = v cc + 0.5v + 20 ma dc input voltage (v i ) ? 0.5v to v cc + 0.5v dc output diode current (i ok ) v o = ? 0.5v ? 20 ma v o = v cc + 0.5v + 20 ma dc output voltage (v o ) ? 0.5v to v cc + 0.5v dc output source or sink current (i o ) 50 ma dc v cc or ground current (i cc or i gnd ) 200 ma storage temperature (t stg ) ? 65 c to + 150 c dc latch-up source or sink current 100 ma supply voltage (v cc ) 2.0v to 3.6v input voltage (v i )0v to v cc output voltage (v o )0v to v cc operating temperature (t a ) ? 40 c to + 85 c minimum input edge rate ( ? v/ ? t) v in from 0.8v to 2.0v v cc @ 3.0v 125 mv/ns symbol parameter v cc t a = + 25 ct a = ? 40 c to + 85 c units conditions (v) typ guaranteed limits v ih minimum high level 3.0 1.5 2.0 2.0 v v out = 0.1v or v cc ? 0.1v v il maximum low level 3.0 1.5 0.8 0.8 v v out = 0.1v input voltage or v cc ? 0.1v v oh minimum high level 3.0 2.99 2.9 2.9 v i out = ? 50 a output voltage 3.0 2.58 2.48 v v in = v il or v ih (note 3) i oh = ? 12 ma v ol maximum low level 3.0 0.002 0.1 0.1 v i out = 50 a output voltage 3.0 0.36 0.44 v v in = v il or v ih (note 3) i ol = 12 ma i in maximum input 3.6 0.1 1.0 a v i = v cc , leakage current gnd i old minimum dynamic 3.6 36 ma v old = 0.8v max (note 5) i ohd output current (note 4) 3.6 ? 25 ma v ohd = 2.0v min (note 5) i cc maximum quiescent 3.6 2.0 20.0 a v in = v cc supply current or gnd v olp quiet output maximum dynamic v ol 3.3 0.2 0.8 v (note 6)(note 7) v olv quiet output minimum dynamic v ol 3.3 ? 0.2 ? 0.8 v (note 6)(note 7) v ihd maximum high level dynamic input voltage 3.3 1.7 2.0 v (note 6)(note 8) v ild maximum low level dynamic input voltage 3.3 1.6 0.8 v (note 6)(note 8)
www.fairchildsemi.com 4 74lvq74 ac electrical characteristics note 9: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). parameter guaranteed by design. ac operating requirements capacitance note 10: c pd is measured at 10 mhz. symbol parameter t a = + 25 ct a = ? 40 c to + 85 c units v cc c l = 50 pf c l = 50 pf (v) min typ max min max f max maximum clock 2.7 50 100 40 mhz frequency 3.3 0.3 100 125 95 t plh propagation delay 2.7 3.5 9.6 16.9 3.5 19.0 ns c dn or s dn to q n 3.3 0.3 3.5 8.0 12.0 2.5 13.0 t phl propagation delay 2.7 4.0 12.6 16.9 3.5 19.0 ns c dn or s dn to q n 3.3 0.3 4.0 10.5 12.0 3.5 13.5 t plh propagation delay 2.7 4.5 9.6 19.0 4.0 23.0 ns cp n to q n or q n 3.3 0.3 4.5 8.0 13.5 4.0 16.0 t phl propagation delay 2.7 3.5 9.6 19.7 3.5 21.0 ns cp n to q n or q n 3.3 0.3 3.5 8.0 14.0 3.5 14.5 t oshl output to output skew (note 9) 2.7 1.0 1.5 1.5 ns t oslh data to output 3.3 0.3 1.0 1.5 1.5 symbol parameter t a = + 25 ct a = ? 40 c to + 85 c units v cc c l = 50 pf c l = 50 pf (v) typ guaranteed minimum t s set-up time, high or low 2.7 1.8 5.0 6.5 ns 3.3 0.3 1.5 4.0 4.5 t h hold time, high or low 2.7 ? 2.4 0.5 0.5 ns d n to cp n 3.3 0.3 ? 2.0 0.5 0.5 t w pulse width 2.7 3.6 7.0 10.0 ns 3.3 0.3 3.0 5.5 7.0 t rec recovery time 2.7 ? 3.0 0 0 ns 3.3 0.3 ? 2.5 0 0 symbol parameter typ units conditions c in input capacitance 4.5 pf v cc = open c pd (note 10) power dissipation capacitance 25 pf v cc = 3.3v
5 www.fairchildsemi.com 74lvq74 physical dimensions inches (millimeters) unless otherwise noted 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow package number m14a
www.fairchildsemi.com 6 74lvq74 low voltage dual d-type positive edge-triggered flip-flop physical dimensions inches (millimeters) unless otherwise noted (continued) 14-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m14d fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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